Static frequency dividers operating up to 150 GHz have been presented using latch modules in hetero-junction bipolar transistor ('HBT') technologies. The article “A novel design of an asymmetric D-latch”, IEEE SiRF, September 2004 describes a 110 GHz wide range static frequency divider, which has a divide ratio of four and consists of two master-slave flip-flops, an input clock buffer and an output buffer. The input buffer improves the input sensitivity at low frequencies by increasing the slew rate of the clock signal. On the other hand its bandwidth limits the maximum operational frequency of the divider.
The article “120-Gb/s Multiplexing and 110-Gb/s Demultiplexing ICs” IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO. 12, December 2004, describes high-speed operation in a latch design using asymmetric current levels in the reading and the holding paths of the latch, the duration of the read period being longer than the store period. Different sizes for transistors in the latch are used to obtain the asymmetric current levels: the emitter size of the transistors in the holding circuit is smaller than the size in the reading circuit. However, the performance at low frequencies is limited by the difference in the size.
The article “110-GHz static frequency divider in SiGe bipolar technology”, IEEE CSICS, October 2005 describes using different DC voltage levels for the clock signal than the inverted-clock signal at the input of the latch. In this way, the performance of the flip-flop is improved at high frequencies. Level shift blocks are used to apply the clock signal to the flip-flop. The voltage level shift can be accomplished by cascaded emitter followers and for large DC offset more than two emitter followers are needed. This article then proposes using the same emitter followers in the Level Shift Block for both Clk and Clk_n paths in the latch. The emitter followers operate at the same current density but a resistor is added in the first emitter follower of the Clk_n path in the Level Shift Block to achieve the DC offset. The performance of this divider depends on the value of the “DC-offset” resistor. With a very large resistance, it is possible to achieve very high operational frequency, but at the expense of the operational frequency range of the divider.